1. Technical Field
The present invention relates to a clock generation circuit generating an output clock in accordance with an input clock state and an imaging device including the clock generation circuit.
Priority is claimed on Japanese Patent Application No. 2011-087533, filed Apr. 11, 2011 and Japanese Patent Application No. 2012-086424, filed Apr. 5, 2012, the content of which is incorporated herein by reference.
2. Background Art
For example, an imaging device configured to capture a high-resolution image at high speed is disclosed in Japanese Unexamined Patent Application, First Publication No. 2009-38781. First, the configuration and operation of the imaging device disclosed in Japanese Unexamined Patent Application, First Publication No. 2009-38781 will be described.
FIG. 32 is a diagram illustrating an overall configuration of a (C)MOS imaging device according to the related art, as disclosed in Japanese Unexamined Patent Application, First Publication No. 2009-38781. An imaging device 1001 includes an imaging unit 1002, a vertical selection unit 1012, a read current source unit 1005, an analog unit 1006, a phase shift unit 1018, a ramp unit 1019, a column processing unit 1015, a horizontal selection unit 1014, an output unit 1017, and a control unit 1020.
In the imaging unit 1002, unit pixels 1003 including a photoelectric conversion element are arranged in a matrix form. The imaging unit 1002 generates a pixel signal corresponding to the amount of an incident electromagnetic wave and outputs the pixel signal to a vertical signal line 1013 installed in each column. When the respective unit pixels 1003 of the imaging unit 1002 are driven, the vertical selection unit 1012 controls a row address or row scanning of the imaging unit 1002 via row control lines 1011. The read current source unit 1005 is a current source that reads the pixel signal from the imaging unit 1002 as a voltage signal. The analog unit 1006 performs amplification or the like, as necessary.
The phase shift unit 1018 is configured by, for example, a delay circuit or the like in which a plurality of delay units (inversion elements) are connected to each other. The phase shift unit 1018 outputs multi-phase clocks (CK0 to CK7) having a constant phase difference from each of the plurality of delay units. The ramp unit 1019 generates a reference signal (ramp wave) increasing or decreasing over time. The column processing unit 1015 includes column AD conversion units 1016 each installed in each column of the imaging unit 1002. The column AD conversion unit 1016 converts an analog pixel signal output for each column from each unit pixel 1003 of the imaging unit 1002 into digital data.
The horizontal selection unit 1014 controls a column address or column scanning of each column AD conversion unit 1016 in the column processing unit 1015. Accordingly, the AD-converted digital data is output sequentially to the output unit 1017 via a horizontal signal line. The control unit 1020 controls each unit of the vertical selection unit 1012, the read current source unit 1005, the analog unit 1006, the phase shift unit 1018, the ramp unit 1019, the column processing unit 1015, the horizontal selection unit 1014, the output unit 1017, and the like.
Next, the configuration of the column AD conversion unit 1016 will be described. The column AD conversion units 1016 each include the same configuration. Each column AD conversion unit 1016 includes a comparison unit 1108, a low-order latch unit 1105, and a column count unit 1103.
The comparison unit 1108 compares an analog pixel signal output from the unit pixel 1003 of the imaging unit 1002 via the vertical signal line 1013 with a reference signal supplied from the ramp unit 1019. When the reference signal is greater than the pixel signal, the comparison unit 1108 outputs a high level (H level). On the other hand, when the reference signal is less than the pixel signal, the comparison unit 1108 outputs a low level (L level). The low-order latch unit 1105 is configured by a plurality of latch circuits. The low-order latch unit 1105 receives a comparison output of the comparison unit 1108 and latches (retains/stores), as the low-order data signal, logic states (low-order phase signals) of the multi-phase clocks (CK0 to CK7), which have a constant phase difference and are output from the phase shift unit 1018, at an inversion timing at which the comparison output is inversed.
The column count unit 1103 is configured by a counter circuit. The column count unit 1103 counts the clock CK7 output from the phase shift unit 1018 as a count clock and obtains a high-order data signal as the count result. Further, the column count unit 1103 obtains digital data corresponding to the magnitude of the pixel signal based on a low-order data signal forming low-order bits and a high-order data signal forming high-order bits.
To achieve synchronization between the high-order bits and the low-order bits, the imaging device inputs one (CK7) of the clocks from the phase shift unit 1018 into the column count unit 1103 via the latch circuits of the low-order latch unit 1105 and uses the clock CK7 as a count clock of the column count unit 1103. That is, when the low-order latch unit 1105 retains the low-order data signal, a change in the clock CK7 output to the column count unit 1103 stops, and thus the column count unit 1103 stops the count process.
A configuration in which a Schmitt trigger circuit is provided between a latch circuit and a counter circuit is disclosed in “Meta-Stability Characteristic of Single-Slope ADC with Time to Digital Convertor for CMOS-Image Sensor”, IEICE Technical Report, by Mhun Shin, Masayuki IKEBE, Junichi MOTOHISA, and Eiichi SANO.
A through-current flowing in a Schmitt trigger circuit is greater than a through-current of a general logic circuit (for example, an inverter circuit). The Schmitt trigger circuit is a kind of feedback circuit. A plurality of passes are formed for a long time in which the through-current flows in accordance with transition (to a ground from a power source) of an input clock. Further, there is a pass in which a larger through-current instantaneously flows. In a case in which the Schmitt trigger circuit is applied to an imaging device, a large direct electric current flows and therefore voltage drop occurs, for example, when the states of latch circuits are changed simultaneously in thousands of columns.
Hereinafter, a case in which a large through-current flows in the Schmitt trigger circuit will be described. FIGS. 33A and 33B are diagrams illustrating an example of the configuration of the Schmitt trigger circuit. The Schmitt trigger circuit shown in FIGS. 33A and 33B includes transistors M1, M2, and M3, which are PMOS transistors, and transistors M4, M5, and M6, which are NMOS transistors.
FIG. 33A shows a through-current flowing when an input voltage VIN is changed from an L state to an H state. When the input voltage VIN is in the L state, the transistors M1, M3, and M5 are in an ON state and the transistors M2, M4, and M6 are in an OFF state. Further, a voltage V1 input into the gates of the transistors M2 and M5 is in the H state and an output voltage VOUT is in the L state.
When the input voltage VIN is changed from the L state to the H state, the transistor M1 is changed from the ON state to the OFF state and the transistor M6 is changed from the OFF state to the ON state. When the transistors M1 and M6 are in a substantially intermediate state of the ON state and the OFF state, a through-current I1 flows via the transistors M1 and M6. There is a delay time in which the change in the voltage V1 propagates to the output voltage VOUT. Therefore, when the through-current I1 flows, the transistor M3 is in the ON state and a through-current I2 flows via the transistors M3 and M6.
The change in the states of the transistors M1 and M6 causes the voltage V1 to be changed from the H state to the L state. For this reason, the transistor M2 is changed from the OFF state to the ON state and the transistor M5 is changed from the ON state to the OFF state. When the transistors M2 and M5 are in a substantially intermediate state of the ON state and the OFF state, a through-current I3 flows via the transistors M2 and M5.
The change in the states of the transistors M2 and M5 causes the output voltage VOUT to be changed from the L state to the H state. For this reason, the transistor M3 is changed from the ON state to the OFF state and the transistor M4 is changed from the OFF state to the ON state. When the transistors M3 and M4 are in a substantially intermediate state of the ON state and the OFF state, a through-current I4 flows via the transistors M3 and M4.
Of the through-currents described above, it is easy for the through-current I2 to be larger than the other through-currents, since the through-current I2 flows in the state where the transistor M3 is in the ON state.
FIG. 33B shows a through-current flowing when an input voltage VIN is changed from an H state to an L state. When the input voltage VIN is in the H state, the transistors M2, M4, and M6 are in an ON state and the transistors M1, M3, and M5 are in an OFF state. Further, the voltage V1 input into the gates of the transistors M2 and M5 is in the L state and an output voltage VOUT is in the H state.
When the input voltage VIN is changed from the H state to the L state, the transistor M1 is changed from the OFF state to the ON state and the transistor M6 is changed from the ON state to the OFF state. When the transistors M1 and M6 are in a substantially intermediate state of the ON state and the OFF state, a through-current I1 flows via the transistors M1 and M6. There is a delay time in which the change in the voltage V1 propagates to the output voltage VOUT. Therefore, when the through-current I1 flows, the transistor M4 is in the ON state and the through-current I2 flows via the transistors M1 and M4.
The change in the states of the transistors M1 and M6 causes the voltage V1 to be changed from the L state to the H state. For this reason, the transistor M2 is changed from the ON state to the OFF state and the transistor M5 is changed from the OFF state to the ON state. When the transistors M2 and M5 are in a substantially intermediate state of the ON state and the OFF state, the through-current I2 flows via the transistors M2 and M5.
The change in the states of the transistors M2 and M5 causes the output voltage VOUT to be changed from the H state to the L state. For this reason, the transistor M3 is changed from the OFF state to the ON state and the transistor M4 is changed from the ON state to the OFF state. When the transistors M3 and M4 are in a substantially intermediate state of the ON state and the OFF state, the through-current I4 flows via the transistors M3 and M4.
Of the through-currents described above, it is easy for the through-current I2 to be larger than the other through-currents, since the through-current I2 flows in the state in which the transistor M4 is in the ON state.